Ivan Sutherland has taught several research seminars on GasP Circuits.
History of GasP related classes:
* Spring 2009: "Self Resetting Logic"
* Fall 2009: "GasP Circuits"
* Fall 2010: GasP Circuits that work"
The seminar materials for Fall 2010 can be found at: https://arc.cecs.pdx.edu/fall10.
Since 2015 we partition designs into
* links, for communication and storage, and
* joints, for computation and flow control,
as indicated in our ASYNC 2015 paper "Naturalized Communication and Testing."
The full-empty protocol between links and joints is generic for self-timed circuit families.
In addition to distinguishing communication and storage from computation and flow control,
we distinguish actions from states - for distributed initialization, test, debug, and characterization.
We developed this link-joint model to enable collaboration with other self-timed design teams,
so we can re-use, exchange, and mix and match different circuit styles in a single system,
enabling each style to shine where it best suits its application.
During Winter 2017, we offered a special CS-ECE seminar in collaboration with Professor Bryant York,
entitled "Practicum in Asynchronous Circuits, Systems, and Algorithms."
Students developed dataflow applications based on links and joints and the full-empty protocol.
Students used the same ideas to go from hardware design to system and algorithm design.
Each application developed by a student in this course has a hardware foundation that scales and
distributes over space and time. Moreover, that hardware foundation can be implemented using a mix
of self-timed circuit families: GasP, Click, quasi-delay-insensitive, and so forth. Reasons for a particular
circuit choice may be as practical as "design re-use" or as sophisticated as "energy efficiency."
We now envision the link-joint model with its full-empty protocol and its local action-state control as
"the new RTL" - a clean and simple interface for hardware-software co-design-test of distributed systems.
We want to use this clean and simple interface to enable computer scientists and electrical engineers
to collaborate and to design and test - jointly - the systems of the future whose computations
- we believe - will be distributed over space and time and will be of a self-timed nature.
This vision, which started at our Winter 2017 seminar, defines our present research and teaching agenda.