ASYNCHRONOUS RESEARCH CENTER

ASYNCHRONOUS RESEARCH CENTER

Publications

News, Talks, and Position Statements

  • ARC movie: Paradigm Shift
  • The New York Times, John Markoff, 19 April 2023: A Tech Industry Pioneer Sees a Way for the U.S. to Lead in Advanced Chips, or download text without pictures from (textOnly).  Ivan Sutherland played a key role in foundational computer technologies. Now he sees a path for America to claim the mantle in “superconducting” chips. […] Mark Horowitz, a Stanford computer scientist who has helped start several Silicon Valley companies, said he was unwilling to discount Dr. Sutherland’s passion for superconducting electronics.“People who’ve changed the course of history are always slightly crazy, you know, but sometimes they’re crazy right,” he said.
  • Ivan’s keynote at the 50th Anniversary of Computing at the University of Utah, 23 March 2023: Single Flux Quantum (SFQ) Digital Electronics (Digital circuits totally distinct from Quantum Computing) is a position statement why the US must train a legion of engineers in SFQ circuit technology to remain competitive in the post-Moore’s law world.
  • ASYNC 2022 Summer School: 3-day on-line seminar given by Rajit Manohar (Yale University), Benjamin Hill (Intel), Montek Singh (University of North Carolina at Chapel Hill), and Marly Roncken, Ebele Esimai, and Ivan Sutherland (Portland State University). Audio presentations and slides are available at https://asyncsymposium.org/async2022. The Portland State presentations cover:
  • Ivan’s position statement for the “Computer Architecture” panel chaired by David Patterson at the ACM Turing Centenary Celebration, July 2012, published as “Viewpoint” in Communications of the ACM, Vol. 55, No. 10, pages 35-36, October 2012: The Tyranny of the Clock (ACM link), and available from our web site at (paper).
  • Ivan Sutherland: Technology and Courage. This text is based on a lecture Ivan gave at Carnegie Mellon University (CMU) in 1982. It was the first, and nearly the only, non-technical lecture he has ever given. His daughter, Juliet, encouraged him to publish it, so that others, especially young people, may garner value from it. In Ivan’s words: “Perhaps experience has something to offer youth.” The text was eventually published by ACM Press in 1991, in the CMU Computer Science 25th Anniversary Commemorative. The version on this web site was reprinted by Sun Microsystems Laboratories with permission of the ACM press, as a courtesy to those who may wish a copy. Enjoy!

Selected Publications

Selected ARC Reports

  • Swetha Mettala Gilla: Distance Constraint Graph: A Graphical Representation for GasP circuits, showing how Relative Timings constrain the Module Distances. This 2009 ARC report extends the 2010 publication by Prasad Joshi (see publications below) to long wire distance models, and introduces the notion of Distance Constraint Graph. This report forms the basis of Swetha’s ASYNC 2010 publication on Long-Range GasP.
  • Willem Mallon and Klaus Ully: High-performance Self-timed Processing Networks. This 2011 ARC report describes how to build a microprocessor, called LEETL, using only simple pipeline controllers.
  • Willem Mallon: Bounded Bundled Data. This 2011 ARC report describes a more general solution approach for data versus control setup and hold time specification and validation, compared to the standard bundled-data self-timed design approach. Willem built this solution into our silicon compiler, ARCwelder. Hoon Park embedded it in his timing verification framework, ARCtimer (see publications below).
  • Ivan Sutherland, Marly Roncken, Navaneeth Jamadagni, Chris Cowan, and Swetha Mettala Gilla: The Weaver, an 8×8 Crossbar Experiment. This 2015 ARC report gives a design overview, circuit schematics, and test measurements for the Weaver, a self-timed 8×8 crossbar experiment built in 40nm CMOS by TSMC. Weaver and Anvil, two separate experiments on this 40nm CMOS chip are the first experiments designed and tested using our new point of view on how to design and test self-timed systems (see ASYNC 2015 publication below). We took the chip with us to ASYNC 2015 for live demos. The ARC has had multiple ongoing student projects that use the Weaver and Anvil to explore and examine self-timed behaviors live. Our 2020 book chapter in Asynchronous Circuit Applications, published by IET under editors Jia Di and Scott C. Smith, uses the Weaver to demonstrate how to design and test high-speed asynchronous circuits, and covers the contents of this 2015 ARC report.

Selected references that we use with asynchronous regularity

  • Cuong Kim Chau: A Hierarchical Approach to Formal Modeling and Verification of Asynchronous Circuits (UT Austin link). or download directly from (PhD thesis). Doctor of Philosophy Thesis, The University of Texas at Austin, 2019.
  • Ad Peeters, Frank te Beest, Mark de Wit, and Willem Mallon: Click Elements: An Implementation Style for Data-Driven Compilation (IEEE link) or download directly from our web site at (paper). In Proc. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pages 3-14, 2010. One of the first (and last) papers on Click circuits and data-driven (as opposed to control-driven) compilation by Philips Handshake Solutions. Willem Mallon, one of the authors of this paper, spent two years at the ARC, and introduced us to both Click and its compiler. During his stay, Willem developed a follow-up compiler version, called ARCwelder, which lies at the basis of a number of our research projects.
  • Ad Peeters and Arjan Bink, Handshake Solutions: Asynchronous circuit technology is on the market (ASYNC 2008 link) or download directly from our web site at (presentation slides) and (abstract). Keynote talk at the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), Newcastle University, UK, 2008.
  • Peter Beerel and Marly Roncken: Low Power and Energy Efficient Asynchronous Design (ASP-JOLPE link) or download directly from (paper). In Journal of Low Power Electronics (JOLPE), Volume 3, Number 3, pages 234-253, December 2007.
  • Ivan Sutherland and Scott Fairbanks: GasP: A Minimal FIFO Control (IEEE link) or download directly from (paper). In Proc. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pages 46-53, 2001. The first paper on GasP circuits published by Sun Microsystems (now Oracle). It received the Best Paper Award at ASYNC 2001. At the ARC, we work extensively with GasP circuits. The Weaver chip (see ARC reports) was designed using so-called 6-4 GasP circuits. These differ from the 4-2 GasP circuits in this first publication in that they have a forward latency, reverse latency, and cycle time of respectively 6, 4, and 6+4=10 (rather than 4, 2, and 4+2=6) gate delays.
  • Jens Sparso and Steve Furber: Introduction to Asynchronous Circuit Design (DTU link) or download directly from our web site at (paper). DTU Compute, Technical University of Denmark, 2020.
  • Kenneth Stevens, Shai Rotem, Ran Ginosar, Peter Beerel, Chris Myers, Kenneth Yun, Rakefet Kol, Charles Dike, and Marly Roncken: An Asynchronous Instruction Length Decoder (IEEE link) or download directly from (paper). In IEEE Journal of Solid-State Circuits, Vol. 36, No. 2, pages 217-228, February 2001.
  • Ivan Sutherland, Bob Sproull, David Harris: Logical Effort: Designing Fast CMOS Circuits (ACM link) or view a summary at (Wikipedia). Morgan Kaufmann Publishers Inc. 1999. Circuits designed at the ARC use transistor sizes that are calculated using the Theory of Logical Effort to obtain (1) sufficiently short rise and fall times that enable us to work in the digital rather than analog domain, (2) correct digital behavior in the presence of (self-timed) loops, and (3) a good first-order path delay model based on counting the number of gates on a path.
  • Marly Roncken: Defect-Oriented Testability for Asynchronous IC’s (IEEE link) or download directly from our web site at (paper).In Proceedings of the IEEE, Vol. 87, No. 2, pages 363-375, February 1999.
  • Kees van Berkel, Ronan Burgess, Joep Kessels, Ad Peeters, Marly Roncken, Frits Schalij, and Rik van de Wiel: A Single-Rail Re-implementation of a DCC Error Detector Using a Generic Standard-Cell Library (IEEE link) or download directly from our web site at (paper). In Proc. Asynchronous Design Methodologies, pages 72-79, 1995. This second version of the low-power DCC error corrector published by Philips Research uses single-rail – also known as bundled-data – handshake protocols. The single-rail protocol and circuit implementations were developed by Ad Peeters as a part of his PhD research.
  • Kees van Berkel, Ronan Burgess, Joep Kessels, Marly Roncken, Frits Schalij, and Ad Peeters: Asynchronous Circuits for Low Power: A DCC Error Corrector (IEEE link) or download directly from our web site at (paper). In IEEE Design & Test of Computers, Vol. 11, Issue 2, pages 22-32, Summer 1994. This first version of the low-power DCC error corrector published by Philips Research uses quasi delay-insensitive handshake circuits.
  • Kees van Berkel, Joep Kessels, Marly Roncken, Ronald Saeijs, and Frits Schalij: The VLSI-programming language Tangram and its translation into handshake circuits (IEEE link) or download directly from our web site at (paper). In Proc. European Design Automation Conference (EDAC), pages 384-389, 1991. One of the early papers about Tangram. The term “VLSI programming” came from Cees Niessen of Philips Research, and refers to the syntax-directed relation between programs in Tangram and the circuits they translate to. The handshake circuits at the time of this publication were quasi delay-insensitive and were used in the first version of the DCC error corrector published in 1994. Later circuit translations applied in the second version of the DCC error corrector, published in 1995, use bundled data protocols.
  • Ivan Sutherland: Micropipelines (ACM link) or download directly from our web site at (paper). In Communications of the ACM, Volume 32, Issue 6, pages 720-738, June 1989.